According to Amazon, the book will be available starting March 11.
Here are some chapter-by-chapter highlights:
- Ch. 2 (Data): After hearing many students saying ``It's too hard!'' we took a closer look and decided that the presentation could be improved by more clearly indicating which sections should be treated as informal discussion and which should be studied as formal derivations (and possibly skipped on first reading). Hopefully, these guideposts will help the students navigate the material, without us reducing the rigor of the presentation.
- Ch. 3 (Machine Programming): It's x86-64 all the way! The entire presentation of machine language is based on x86-64. Now that even cellphones run 64-bit processors, it seemed like it was time to make this change. Eliminating IA32 also freed up space to put floating-point machine code back in (it was present in the 1st edition and moved to the web for the 2nd edition). We generated a web aside describing IA32. Once students know x86-64, the step (back) to IA32 is fairly simple.
- Ch. 4 (Architecture): Welcome to Y86-64! We made the simple change of expanding all of the data widths to 64 bits. We also rewrote all of the machine code to use x86-64 procedure conventions.
- Ch. 5 (Optimization): We brought the machine-dependent performance optimization up to date based on more recent versions of x86 processors. The web aside on SIMD programming has been updated for AVX2. This material becomes even more relevant as industry looks to the SIMD instructions to juice up performance.
- Ch. 7 (Linking): Linking as been updated for x86-64. We expanded the discussion of position-independent code and introduce library inter positioning.
- Ch. 8 (Exceptional Control Flow): We have added a more rigorous treatment of signal handlers, including signal-safe functions.
- Ch. 11 (Network Programming): We have rewritten all of the code to use new libraries that support protocol-independent and thread-safe programming.
- Ch. 12 (Concurrent Programming): We have increased our coverage of thread-level parallelism to make programs run faster on multi-core processors.
